FPGA Architecture

Intel FPGA Architechture

FPGA Logic Array Blocks (LABs) are made up of Logic Elements (LEs) or Adaptive Logic Modules (ALMs). Each of these logic blocks consists of Look Up Tables(LUTs), and registers.

Look Up Tables(LUTs)

Creating sum of products function out of combinatorial logic in an FPGA. FPGA uses four or more input LUTs to create complicated functions. A LUT is made up of a series of cascaded multiplexers where the LUT inputs are used as the select lines. The inputs to the multiplexers are programmed as hugh ir low logic levels. The logic is called a Look Up Table.

Programmable Register

This is the synchronous part of an Logic Elements. It is driven by a global device clock. Aynchronous control signals of the registers(ex. clear, reset) can be generated by other logic or come from an I/O pin. The output of the register can drive out of the LE to the device's routing channels, or be fed back into the LUT. Register could be bypassed for a combinatorial logic. LUT could also be bypassed and only register could be used for memory. This flexibility in the output stage of the LE makes it extremely efficient.

Carry and Register chains

Chains carry bits between LEs. Register outputs can chain to other LE registers in LAB toform LUT independent shift registers.

Register packing FPGA LEs can be configured to perform a function called Register packing. Two seperate functions can be output from a single LE, one from the carry and chain logic and the other from the output register. This helps in saving device resources.

Adaptive Logic Module (ALM)

Replacement for the LEs from traditional FPGAs due to lack of cascading and feedback which is necessary to generate functions with more inputs than are available. It improves performance and resource utilization. ALMS comprise of 2 to 4 output registers to provide even more options for logic chaining, register packing, and generating multiple functions within a single logic block. ALMs also have dedicated built-in hardware adder blocks. The main differentiator between LEs and LUTs is a LUT. The LUT in an ALM is an Adaptive LUT or ALUT. ALUT can be split and configured into different sized LUTs to accommodate two separate functions.

FPGA Routing: In an FPGA, the LABs are all arranged into a large array. Programmable routing is placed in the spaces between LABs, similar to the streets in a city.

Intel Products

Intel delivers a broad portfolio of custom logic solutions such as FPGAs, SoCs, structured ASICs, and CPLDs together with software tools, intellectual property (IP), embedded processors, customer support, and technical training.

Intel FPGAs

Intel Agilex FPGAs

: This FPGA family integrate an 10nm FPGA. Intel Agilex SoC FPGAs integrate the quad-core Arm Cortex-A53 processor. Applications: wide range of compute and bandwidth intensive applications.

INTEL AGILEX F-SERIES FPGAs AND SoCs

: This FPGA and SoC FPGA family bring together transceiver support, digital signal processing (DSP) capabilities along with an option to integrate the quad-core Arm Cortex-A53 processor. Applications: wide range of data center, networking, and edge applications.

INTEL AGILEX I-SERIES SoC FPGAs

: This FPGA family is optimized for high-performance processor interface and bandwidth-intensive applications.

INTEL AGILEX M-SERIES SoC FPGAs

: This SoC FPGA family is optimized for compute and memory intensive applications.

Intel Stratix Series

: This FPGA and SoC family enables you to deliver high-performance, state-of-the-art products to market faster with lower risk and higher productivity.

Intel Arria Series

: This device family delivers performance and power efficiency in the midrange. The Intel Arria 10 FPGAs and SoCs are ideal for the end market applications such as Wireless, Cloud Service and Storage, Broadcast.

Intel Cyclone Series

: The Intel Cyclone FPGA series is built to meet your low-power, cost-sensitive design needs, enabling you to get to market faster.

Intel MAX Series

: This non-volatile FPGA family is optimized for a wide range of high-volume, cost-sensitive applications, such as Automotive, Industrial, Communications.

Intel eASIC Devices

Intel eASIC devices are structured ASICs, an intermediary technology between FPGAs and standard-cell ASICs, that provide lower unit cost and lower power compared to FPGAs. These devices provide faster time to market and lower non-recurring engineering (NRE) cost compared to standard-cell ASICs. Different eASIC amilies are: Intel eASIC N5X Devices (Comes with Arm Cortex-A53 hard processor system), Intel eASIC N3XS Devices, Intel eASIC N3X and N2XT Devices.