My Notes Wiki
  • Documentation
  • Data Science
    • Data Science Bootcamp Udemy Course
  • Digital Design by Morris Mano
    • Digital Systems and Binary Numbers
    • Boolean Algebra and Logic Gates
    • Gate‐Level Minimization
    • Combinational Circuits
    • Synchronous Sequential Logic
    • Registers and Counters
    • Memory and Programmable Logic
    • Design at the Register Transfer Level
  • FPGA
    • Overview
    • Hardware
      • FPGA History
      • FPGA Architecture
      • Static Timing Analysis
      • Clock Domain Crossing
    • Protocols
      • UART
      • AXI
      • SPI
      • PCIE
    • Peripherals & IPs
      • Memories
      • RAM
      • DDR
      • DDR3
      • Flash
      • EMMC
      • Gigabit Ethernet
      • DMA
    • Software & Tools
      • verilog
    • Links & References
  • HLS
    • High-Level Synthesis Prerequisites(UG998)
    • Vitis High-Level Synthesis(UG1399)
    • Vivado High-Level Synthesis Tutorial(UG871)
  • Image Processing
  • Programming Languages
    • C
    • Cpp
    • HDL
      • HDL Basics
      • Verilog
      • SystemVerilog
      • VHDL
      • Verilog Codes
    • Python
  • Vitis
    • Vitis
  • Zynq
    • zynq
Powered by GitBook
On this page
  • Table of Contents
  • Digital Systems and Binary Numbers
  • Boolean Algebra and Logic Gates
  • Gate‐Level Minimization
  • Combinational Circuits
  • Synchronous Sequential Logic
  • Registers and Counters
  • Memory and Programmable Logic
  • Design at the Register Transfer Level

Digital Design by Morris Mano

These are the notes of the book "Digital Logic Design by Morris Mano" written/compiled by Maitreya Ranade.

Table of Contents

Digital Systems and Binary Numbers

Boolean Algebra and Logic Gates

Gate‐Level Minimization

Combinational Circuits

Synchronous Sequential Logic

Registers and Counters

Memory and Programmable Logic

Design at the Register Transfer Level


PreviousData Science Bootcamp Udemy CourseNextDigital Systems and Binary Numbers

Last updated 2 years ago